There is an interesting debate about feature size though. Devices on silicon for a long long time were essentially 2D, patterns on the top surface of Silicon. "Feature size" in this environment directly translated into area which directly translated into the die size.
As features got smaller you started getting 'trench fets' and other tricks to increase the effective size of the gates so that leakage current wasn't insane. So at what point then do the circuit elements become fully vertical, which is to say that viewed from the 'top' the transistor is 10 nm on a side but vertically its 22 nm 'tall' ?
And other tricks where the silicon layers are separately tested and 'thinned' and then packaged as a sandwich for
final testing with ion implanters creating the vias between the connecting layers.
Really interesting work in that sort of stuff going on.
There is an interesting debate about feature size though. Devices on silicon for a long long time were essentially 2D, patterns on the top surface of Silicon. "Feature size" in this environment directly translated into area which directly translated into the die size.
As features got smaller you started getting 'trench fets' and other tricks to increase the effective size of the gates so that leakage current wasn't insane. So at what point then do the circuit elements become fully vertical, which is to say that viewed from the 'top' the transistor is 10 nm on a side but vertically its 22 nm 'tall' ?
And other tricks where the silicon layers are separately tested and 'thinned' and then packaged as a sandwich for final testing with ion implanters creating the vias between the connecting layers.
Really interesting work in that sort of stuff going on.