This doesn't make sense to me. You don't have to use negative voltages to encode ternary. You can just use three different positive voltages, if you like. 0V = 0, +3V = 1, +6V = 2.
The main problem is that if you are minimizing the voltage to the minimum that can be safely distinguished for binary, you must, by necessity, be introducing twice that voltage to introduce another level. You can't just cut your already-minimized voltage in half to introduce another level; you already minimized the voltage for binary.
50 years ago this may not have been such a problem, but now that we care a lot, lot more about the power consumption of our computing, and a lot of that power consumption is based on voltage (and IIRC often super-linearly), so a tech that requires us to introduce additional voltage levels pervasively to our chips is basically disqualified from the very start. You're not sticking one of these in your server farm, phone, or laptop anytime soon.
Indeed that's how nearly all NAND flash works nowadays, early SLC media was binary with each cell set to a low or high voltage, but as density increased they started using more voltages inbetween to encode multiple bits per cell. The current densest NAND uses 16 different positive voltage states to encode 4 bits per cell.
Most "SLC" and "MLC" that's sold is actually TLC/QLC hardware that's only using a subset of the voltage levels available. It ends up being significantly cheaper due to the economies of scale in manufacturing.
Yep, if you ever come accross the term "pSLC" (Pseudo-SLC) that means the underlying hardware is capable of running in MLC/TLC/QLC mode, but the controller firmware has been configured to only use the lowest and highest voltage state in each cell.
Some SSD controllers will also reassign regions of flash to different modes on the fly, the drives unused capacity can be used internally as a very fast pSLC write cache, and then as the drive fills up those cells incrementally get switched over to the native TLC/QLC mode.
Very interesting. I would have thought the overhead from the memory controller would negate all savings, but I know very little about modern cell design.
If you want to do it in a single step, you need 8 analogic comparators at the output of the memory, and one level of "and" and "or" gates to solve each bit.
Most ADCs use a single comparator + OpAmp and convert the value in 3 steps. But that would make your memory slower.
Either way, the task of converting it does not fall over the controller.
Voltages are always measure relative to each other. In ops example -3V to +3V has 6V difference just as 0V to 6V does and the arcing is the same.
Op didn’t specify any particular voltage but you should get the example. You need more voltage between the highest and lower states to differentiate the signals compared to binary. It can work well but only in circuits where there’s already very low leakage (flash mentioned as another reply is a great example).
While true, being negative in a semiconductor system is very relevant though because any P-N junction is a diode. So your ability to propagate current (and thus downstream voltages) does depend on the voltages all pointing the right direction.
note: I am aware that strictly speaking a CPU isn't transistors, but it is a lot of variously doped silicon still.
Yes, but then you have to use a lot more complex electronics and production tolerances, as now you'd need to either distribute voltage reference for intermediate level all over the board, which essentially makes it exactly same system as with negative voltage, but with the third wire becoming ground; the same concept but worse implementation, or make circuits able able to discriminate between two different levels, this will be both difficult in terms of implementing the circuit, and will also lead to enormous energy waste, as part of your transistors will have to be half open (jinda similar similar to ECL logic, but worse).
Practically it is convenient I think if your ground is third little round prong on the power cord.
I wonder if this is why they suggested a negative voltage. Even though voltages are secretly relative under the hood, it seems like it could simplify things to have two directionally different voltages.
Many reasons. For example, using negative voltage will reduce DC component in the wires, that will improve reliability over long lines, as now all you need is to sense the polarity of the signal, not the level. You'd also need high power reference voltage (for "1") wire going all over the board, which will be nasty polluted with uncorrelated switching noise, will sag in uncorellated way with respect to the "2" (Vcc wire) etc.
Except in the analog world its not so clear, you can't just say +3V=1. What if its 3.7V? or 4.5V? Early tools weren't that accurate either so you needed more range to deal with it.
It should be stated as ranges for clarity. It’s never an absolute voltage (quantum mechanics itself won’t round that nicely). Although this is also true of binary. >x volts = 1 otherwise 0 volt n binary. Same thing in ternary just with 3 ranges.
Yeah at some point you have to deal with the transition between the clean conceptual world of digit computing and deal with the fact a circuit can't instantly transition between 0v and 3.3v/5v/whatever level your signal operates at.
