They contain hundreds up to many thousands of FPGAs. Using support dev tools, you can take a large ASIC design and partition it over these FPGAs.
We once used four interconnected machines like these to emulate a large superscalar, OOO CPU design. It took a few days, but could go from release of reset to loaded OS. Something impossible with a SW simulation. Fun times.
https://www.cadence.com/en_US/home/tools/system-design-and-v...
https://eda.sw.siemens.com/en-US/ic/precision/
They contain hundreds up to many thousands of FPGAs. Using support dev tools, you can take a large ASIC design and partition it over these FPGAs.
We once used four interconnected machines like these to emulate a large superscalar, OOO CPU design. It took a few days, but could go from release of reset to loaded OS. Something impossible with a SW simulation. Fun times.