> Intel compares the performance to a Nios II/e (it's 4x faster!), but at 6 cycles/instruction, no multiplier, one bit per clock shifter (IOW: no barrel shifter), the II/e is about the worst little CPU you can imagine.
I think the memory system in that example has a 3 cycle memory access latency, and the CPU waits for one instruction to arrive before requesting the next one. I'm almost surprised that they manage 0.464!
The Coremark score doesn't make any sense indeed. Where did you find these numbers?
> I think the memory system in that example has a 3 cycle memory access latency, and the CPU waits for one instruction to arrive before requesting the next one. I'm almost surprised that they manage 0.464!
That seems unbelievably large for V/m. A VexRISCV using 352 Cyclone V ALMs gives 10% better dhrystone than V/m, and a configuration using 1764 ALMs gives you 1.2 DMIPS/MHz, I and D caches, branch prediction, Supervisor mode, MMU -- full Linux kernel capability.
Okay, let's do a better one.
On a stratix 10:
II/e uses 414 units, II/f uses 1006 units, and V/m uses 1580.
II/e gets .107 DMIPS/MHz, II/f gets .753, and V/m gets .464.
Coremark for II/e is 19, for II/f is 229, and for V/m is... only 16?
II/e runs at 320MHz, II/f at 300MHz, and V/m at 362MHz.
Overall, not looking great for the cost, but if you really want RISC-V I'm sure that has value.
And what's with CoreMark? I do notice they gave the II/f a big cache for that test.