It's a pretty smart decision for them. They save who knows how many millions/billions in supporting a very proprietary ISA and the resulting proprietary software stack.
I have no idea how you arrived at a millions/billions number.
The Nios II family has existed for years, with very little ongoing development. FPGA soft cores don't go above the ~1.5 Dhrystone MIPS per MHz because the increased complexity to go above the 5-stage pipeline doesn't play well with FPGA-style logic. The Nios II/f already occupied that space.
Nios II is more than hardware. How do you run code on it?
They have to maintain all the compiler stuff, all the libraries, all the related OS kernel and library changes.
The core also needs updates to keep it current with newer hardware interfaces.
With just a team of 50 people to do all these things, that's a minimum of 10-20 million per year. That's not including the initial development team being much larger. Over a decade or two, hundreds of millions or more is not unlikely.
Like I wrote, the Nios II is old. There’s barely any development going on. The compiler has a few bug fixes here and there.
The libraries are all in C, CPU agnostic, and primarily there to support various Intel Platform Designer modules (you can easily verify that by looking at the BSP). None of that goes away when switching to RISC-V.
I have no idea what you mean with “newer hardware interfaces”, especially in the context of reducing cost: when using RISC-V, you’ll have these newer hardware interfaces (whatever you mean by it) just the same.
It’s not about how much money it costs to maintain the Nios infrastructure, its about how much they’ll save by adding(!) an extra CPU to support.
Somewhat aside: most FPGA IP development of Intel happens in Malesia, so don’t assume US salaries… But if you estimate it at $10M-$50M, shall we agree that writing “billions” was more than a bit over the top?
Intel will save a tiny bit on not having to maintain a custom GNU toolchain. That’s about it.
